USING VLSI TO REDUCE SERIALIZATION AND MEMORY TRAFFIC IN SHARED MEMORY PARALLEL COMPUTERS.

The NYU Ultracomputer is an architecture for a large scale MIMD (Multiple Instruction stream, Multiple Data stream) shared memory parallel computer that may be viewed as a column of processors and a column of memory modules connected by a rectangular network of enhanced two by two buffered crossbars. The primary novelty of the design is the ability of the network to combine multiple requests directed at the same memory location, including a new coordination request, fetch-and-add. This permits task coordination to be achieved in a highly parallel manner. This report reviews the Ultracomputer architecture and system design and describes the VLSI enhanced buffered crossbars that are the key to the highly parallel behavior.