Utilisation of input compatibilities alleviates test costs in many applications such as reducing linear feedback shift register (LFSR) size, and scan tree construction among others. Correlation among inputs, identified based on a test set analysis, can be exploited by driving the circuit inputs through fewer channels. The reduction in the number of channels, which is dictated by the number of compatible input groups, determines the extent of test cost savings thus attained. The utilisation of inverse compatibility along with direct compatibility of inputs helps reduce test costs further. The don't care bits in a test set, however, complicate the identification of valid compatibility groups that consist of both pairwise directly and pairwise inversely compatible inputs, as conflicts may arise during the specification of these don't care bits, leading to an invalid compatibility class. Here, the authors formally model inverse compatibility for the first time, tackling the challenge induced by the specification of don't care bits in the process of identification of compatible group, thus enabling the utilisation of inverse compatibilities along with direct compatibilities. The hyper-graph-based modelling that is introduced here enables the exploitation of the full potential of inverse compatibilities. The applications that rely on input compatibility can, thus, greatly benefit from the techniques presented here in attaining higher test cost savings.
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering