Vertical flash memory cell with nanocrystal floating gate for ultradense integration and good retention

Joy Sarkar, Sagnik Dey, Davood Shahrjerdi, Sanjay K. Banerjee

Research output: Contribution to journalArticle

Abstract

We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 °C. The cell shows a large memory window of ∼1 V and endurance of more than 105 cycles.

Original languageEnglish (US)
Pages (from-to)449-451
Number of pages3
JournalIEEE Electron Device Letters
Volume28
Issue number5
DOIs
StatePublished - May 2007

Keywords

  • Flash
  • Memory
  • Nanocrystal
  • Pillar
  • Retention
  • Sidewall
  • Vertical

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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