The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 14 F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V, endurance > 105 cycles, and retention beyond 105 s is reported.
|Original language||English (US)|
|Journal||Applied Physics Letters|
|State||Published - 2007|
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)