TY - GEN
T1 - Vertical IP Protection of the Next-Generation Devices
T2 - 2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021
AU - Rai, Shubham
AU - Garg, Siddharth
AU - Pilato, Christian
AU - Herdt, Vladimir
AU - Moussavi, Elmira
AU - Sisejkovic, Dominik
AU - Karri, Ramesh
AU - Drechsler, Rolf
AU - Merchant, Farhad
AU - Kumar, Akash
N1 - Publisher Copyright:
© 2021 EDAA.
PY - 2021/2/1
Y1 - 2021/2/1
N2 - With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from system-level down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.
AB - With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both-the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives-from system-level down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.
UR - http://www.scopus.com/inward/record.url?scp=85111038055&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85111038055&partnerID=8YFLogxK
U2 - 10.23919/DATE51398.2021.9474132
DO - 10.23919/DATE51398.2021.9474132
M3 - Conference contribution
AN - SCOPUS:85111038055
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1905
EP - 1914
BT - Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 1 February 2021 through 5 February 2021
ER -