@inproceedings{726d77e4eacd4b22a8c72e8100689069,
title = "Vertically-addressed test structures (VATS) for 3D IC variability and stress measurements",
abstract = "We propose a new test array architecture - vertically-addressed test structures (VATS) - to experimentally characterize the within-tier and tier-to-tier process variations and through-silicon via (TSV) induced stress in 3D integrated circuits (ICs). The proposed VATS architecture utilizes the benefits of 3D integration to simultaneously provide high density, low I/O pin utilization, and high fidelity. A test chip featuring eight VATS arrays (>15,000 active devices) has been designed and fabricated in a two-tier, 130-nm 3D IC technology. Simulation results highlight the advantages of the proposed VATS architecture compared to conventional 2D test arrays.We also propose a radial filtering scheme to discriminate between process variations and the impact of TSV-induced stress in 3D ICs.",
keywords = "3D integrated circuit, test structures, variability",
author = "Conor O'Sullivan and Levine, {Peter M.} and Siddharth Garg",
year = "2013",
doi = "10.1109/ISQED.2013.6523596",
language = "English (US)",
isbn = "9781467349536",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "96--103",
booktitle = "Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013",
note = "14th International Symposium on Quality Electronic Design, ISQED 2013 ; Conference date: 04-03-2013 Through 06-03-2013",
}