TY - GEN
T1 - Virtualizing virtual channels for increased network-on-chip robustness and upgradeability
AU - Evripidou, Marios
AU - Nicopoulos, Chrysostomos
AU - Soteriou, Vassos
AU - Kim, Jongman
PY - 2012
Y1 - 2012
N2 - The Network-on-Chip (NoC) router buffers are instrumental in the overall operation of Chip Multi-Processors (CMP), because they facilitate the creation of Virtual Channels (VC). Both the NoC routing algorithm and the CMP's cache coherence protocol rely on the presence of VCs within the NoC for correct functionality. In this article, we introduce a novel concept that completely decouples the number of supported VCs from the number of VC buffers physically present in the design. Virtual Channel Renaming enables the virtualization of existing virtual channels, in order to support an arbitrarily large number of VCs. Hence, the CMP can (a) withstand the presence of faulty VCs, and (b) accommodate routing algorithms and/or coherence protocols with disparate VC requirements. The proposed VC Renamer architecture incurs minimal hardware overhead to existing NoC designs and is shown to exhibit excellent performance without affecting the router's critical path.
AB - The Network-on-Chip (NoC) router buffers are instrumental in the overall operation of Chip Multi-Processors (CMP), because they facilitate the creation of Virtual Channels (VC). Both the NoC routing algorithm and the CMP's cache coherence protocol rely on the presence of VCs within the NoC for correct functionality. In this article, we introduce a novel concept that completely decouples the number of supported VCs from the number of VC buffers physically present in the design. Virtual Channel Renaming enables the virtualization of existing virtual channels, in order to support an arbitrarily large number of VCs. Hence, the CMP can (a) withstand the presence of faulty VCs, and (b) accommodate routing algorithms and/or coherence protocols with disparate VC requirements. The proposed VC Renamer architecture incurs minimal hardware overhead to existing NoC designs and is shown to exhibit excellent performance without affecting the router's critical path.
UR - http://www.scopus.com/inward/record.url?scp=84867753932&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84867753932&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2012.44
DO - 10.1109/ISVLSI.2012.44
M3 - Conference contribution
AN - SCOPUS:84867753932
SN - 9780769547671
T3 - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
SP - 21
EP - 26
BT - Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
T2 - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Y2 - 19 August 2012 through 21 August 2012
ER -