VLSI testing based security metric for IC camouflaging

Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.

Original languageEnglish (US)
Title of host publicationProceedings - 2013 IEEE International Test Conference, ITC 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479908592
DOIs
StatePublished - 2013
Event44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States
Duration: Sep 10 2013Sep 12 2013

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

Other44th IEEE International Test Conference, ITC 2013
CountryUnited States
CityAnaheim, CA
Period9/10/139/12/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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