VLSI testing based security metric for IC camouflaging

Jeyavijayan Rajendran; Ozgur Sinanoglu; Ramesh Karri

doi:10.1109/TEST.2013.6651879

VLSI testing based security metric for IC camouflaging

Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.

Original language	English (US)
Title of host publication	Proceedings - 2013 IEEE International Test Conference, ITC 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9781479908592
DOIs	https://doi.org/10.1109/TEST.2013.6651879
State	Published - 2013
Event	44th IEEE International Test Conference, ITC 2013 - Anaheim, CA, United States Duration: Sep 10 2013 → Sep 12 2013

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Other

Other	44th IEEE International Test Conference, ITC 2013
Country/Territory	United States
City	Anaheim, CA
Period	9/10/13 → 9/12/13

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2013.6651879

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VLSI testing based security metric for IC camouflaging. / Rajendran, Jeyavijayan; Sinanoglu, Ozgur ; Karri, Ramesh.
Proceedings - 2013 IEEE International Test Conference, ITC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6651879 (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rajendran, J, Sinanoglu, O & Karri, R 2013, VLSI testing based security metric for IC camouflaging. in Proceedings - 2013 IEEE International Test Conference, ITC 2013., 6651879, Proceedings - International Test Conference, Institute of Electrical and Electronics Engineers Inc., 44th IEEE International Test Conference, ITC 2013, Anaheim, CA, United States, 9/10/13. https://doi.org/10.1109/TEST.2013.6651879

@inproceedings{2fce8a6060e046468dfd45183f09c2ab,

title = "VLSI testing based security metric for IC camouflaging",

abstract = "An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.",

author = "Jeyavijayan Rajendran and Ozgur Sinanoglu and Ramesh Karri",

year = "2013",

doi = "10.1109/TEST.2013.6651879",

language = "English (US)",

isbn = "9781479908592",

series = "Proceedings - International Test Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - 2013 IEEE International Test Conference, ITC 2013",

note = "44th IEEE International Test Conference, ITC 2013 ; Conference date: 10-09-2013 Through 12-09-2013",

}

TY - GEN

T1 - VLSI testing based security metric for IC camouflaging

AU - Rajendran, Jeyavijayan

AU - Sinanoglu, Ozgur

AU - Karri, Ramesh

PY - 2013

Y1 - 2013

N2 - An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.

AB - An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor.

UR - http://www.scopus.com/inward/record.url?scp=84891544717&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84891544717&partnerID=8YFLogxK

U2 - 10.1109/TEST.2013.6651879

DO - 10.1109/TEST.2013.6651879

M3 - Conference contribution

AN - SCOPUS:84891544717

SN - 9781479908592

T3 - Proceedings - International Test Conference

BT - Proceedings - 2013 IEEE International Test Conference, ITC 2013

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 44th IEEE International Test Conference, ITC 2013

Y2 - 10 September 2013 through 12 September 2013

ER -

VLSI testing based security metric for IC camouflaging

Abstract

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ASJC Scopus subject areas

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