TY - GEN
T1 - Voltage-tunable stochastic computing with magnetic bits
AU - Rangarajan, N.
AU - Parthasarthy, A.
AU - Kani, N.
AU - Rakheja, S.
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/8/10
Y1 - 2017/8/10
N2 - In this paper, we model and design spintronic circuits that exploit the inherent stochasticity of nanomagnetic dynamics, while providing ultra-low-energy (∼ 3-5 aJ/bit) and ultra-low-power (< 106 W/m2) operation.
AB - In this paper, we model and design spintronic circuits that exploit the inherent stochasticity of nanomagnetic dynamics, while providing ultra-low-energy (∼ 3-5 aJ/bit) and ultra-low-power (< 106 W/m2) operation.
UR - http://www.scopus.com/inward/record.url?scp=85034640695&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034640695&partnerID=8YFLogxK
U2 - 10.1109/INTMAG.2017.8008050
DO - 10.1109/INTMAG.2017.8008050
M3 - Conference contribution
AN - SCOPUS:85034640695
T3 - 2017 IEEE International Magnetics Conference, INTERMAG 2017
BT - 2017 IEEE International Magnetics Conference, INTERMAG 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE International Magnetics Conference, INTERMAG 2017
Y2 - 24 April 2017 through 28 April 2017
ER -