Wear-aware adaptive routing for networks-on-chips

Arseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Chip-multiprocessors are facing worsening reliability due to prolonged operational stresses, with their tile-interconnecting Network-on-Chip (NoC) being especially vulnerable to wearout-induced failure. To tackle this ominous threat we present a novel wear-aware routing algorithm that continuously considers the stresses the NoC experiences at runtime, along with temperature and fabrication process variation metrics, steering traffic away from locations that are most prone to Electromigration (EM)- and Hot-Carrier Injection (HCI)-induced wear. Under realistic applications our wear-aware algorithm yields 66% and 8% average increases in mean-time-to-failure for EM and HCI, respectively.

Original languageEnglish (US)
Title of host publicationProceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
EditorsDiana Marculescu, Andre Ivanov, Partha Pratim Pande, Jose Flich
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450333962
DOIs
StatePublished - Sep 28 2015
Event9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015 - Vancouver, Canada
Duration: Sep 28 2015Sep 30 2015

Publication series

NameProceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015

Other

Other9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015
Country/TerritoryCanada
CityVancouver
Period9/28/159/30/15

Keywords

  • Electromigration (EM)
  • Hot-Carrier Injection (HCI)
  • Lifetime
  • Network-on-chip
  • Reliability
  • Routing algorithm

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Wear-aware adaptive routing for networks-on-chips'. Together they form a unique fingerprint.

Cite this