Workload-driven selective hardening of control state elements in modern microprocessors

Michail Maniatakos, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We present a method for selective hardening of control state elements against soft errors in modern microprocessors. In order to effectively allocate resources, our method seeks to rank the control state elements based on their susceptibility, taking into account the high degree of architectural masking inherent in modern microprocessors. The novelty of our method lies in the way this ranking is computed. Unlike methods that compute the architectural vulnerability of registers based on high-level simulations on performance models, our method operates at the Register Transfer (RT-) Level and is, therefore, more accurate. In contrast to previous RT-Level methods, however, it does not rely on extensive transient fault injection campaigns and lengthy executions of workloads to completion, which may make such analysis prohibitive. Instead, it monitors the behavior of key global microprocessor signals in response to a progressive stuckat fault injection method during partial workload execution. Experimentation with the Scheduler module of an Alpha-like microprocessor corroborates that our method generates a near-optimal ranking, yet is several orders of magnitude faster.

Original languageEnglish (US)
Title of host publicationProceedings - 28th IEEE VLSI Test Symposium, VTS10
Number of pages6
StatePublished - 2010
Event28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States
Duration: Apr 19 2010Apr 22 2010

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Other28th IEEE VLSI Test Symposium, VTS10
Country/TerritoryUnited States
CitySanta Cruz, CA

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering


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