TY - GEN
T1 - Xel-FPGAs
T2 - 42nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2023
AU - Prabakaran, Bharath Srinivas
AU - Mrazek, Vojtech
AU - Vasicek, Zdenek
AU - Sekanina, Lukas
AU - Shafique, Muhammad
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Generation and exploration of approximate circuits and accelerators has been a prominent research domain to achieve energy-efficiency and/or performance improvements. This research has predominantly focused on ASICs, while not achieving similar gains when deployed for FPGA-based accelerator systems, due to the inherent architectural differences between the two. In this work, we propose a novel framework, Xel-FPGAs, which leverages statistical or machine learning models to effectively explore the architecture-space of state-of-the-art ASIC-based approximate circuits to cater them for FPGA-based systems given a simple RTL description of the target application. We have also evaluated the scalability of our framework on a multi-stage application using a hierarchical search strategy. The Xel-FPGAs framework is capable of reducing the exploration time by up to 95%, when compared to the default synthesis, place, and route approaches, while identifying an improved set of Pareto-optimal designs for a given application, when compared to the state-of-the-art. The complete framework is open-source and available online at https://github.com/ehw-fit/xel-fpgas.
AB - Generation and exploration of approximate circuits and accelerators has been a prominent research domain to achieve energy-efficiency and/or performance improvements. This research has predominantly focused on ASICs, while not achieving similar gains when deployed for FPGA-based accelerator systems, due to the inherent architectural differences between the two. In this work, we propose a novel framework, Xel-FPGAs, which leverages statistical or machine learning models to effectively explore the architecture-space of state-of-the-art ASIC-based approximate circuits to cater them for FPGA-based systems given a simple RTL description of the target application. We have also evaluated the scalability of our framework on a multi-stage application using a hierarchical search strategy. The Xel-FPGAs framework is capable of reducing the exploration time by up to 95%, when compared to the default synthesis, place, and route approaches, while identifying an improved set of Pareto-optimal designs for a given application, when compared to the state-of-the-art. The complete framework is open-source and available online at https://github.com/ehw-fit/xel-fpgas.
KW - Accelerator
KW - Approximate Computing
KW - Arithmetic Units
KW - ASIC
KW - FPGA
KW - Models
KW - Regression
KW - Synthesis
UR - http://www.scopus.com/inward/record.url?scp=85181397854&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85181397854&partnerID=8YFLogxK
U2 - 10.1109/ICCAD57390.2023.10323678
DO - 10.1109/ICCAD57390.2023.10323678
M3 - Conference contribution
AN - SCOPUS:85181397854
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
BT - 2023 42nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 28 October 2023 through 2 November 2023
ER -